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Floorplan (microelectronics)
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Mock floorplan in an IC layout editor window
In electronic design automation, a floorplan of an integrated circuit is a schematic representaion of tentative placement of its major functional blocks.
In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to chip design.
Depending on the design methodology, the actual notions of floorplan may differ.
[edit] Mathematical models and optimization problems related to floorplans
In some approaches floorplan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects, etc.
Finding good floorplans has been a research area in combinatorial optimization. Most of problems related to finding optimal floorplans are NP-hard, i.e., require vast computational resources. Therefore the most common approach is to use various optimization heuristics for finding good solutions.
Another approach is to restrict design methodology to certain classes of floorplans, such as sliceable floorplans, see below.
Floorplanning is the act of designing of a floorplan, which is a kind of bird's-eye view of a structure.
[edit] Electronic design automation
In electronic design automation, floorplanning takes in some of the geometrical limitations in a design. Examples of this are:
bonding pads for contacting off-chip (often using wire bonding) are normally located at the circumference of the chip;
line drivers often have to be located as close to bonding pads as possible;
chip area is therefore in some cases given a minimum area in order to fit in the required number of pads;
areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit;
purchased intellectual property blocks (such as a processor core) come in ready defined area blocks;
some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.
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